In recent years, there has been an insatiable desire for faster computer processing data throughputs because cutting-edge computer applications are becoming more and more complex, placing ever increasing demands on microprocessing systems. The microprocessors in these systems may have very rapid cycle times and be capable of manipulating a great amount of data very quickly. The time to access the DRAM memories to which these microprocessors are coupled, however, may be considerably higher than the cycle time of the microprocessor and can vary dramatically based on the extant conditions at the time of the memory access.
In order to ameliorate the bottleneck imposed by the relatively long and variable access time to memory, memory hierarchies utilizing cache memories have been implemented in conjunction with microprocessors. Cache memory augments the data storage function of main memory by providing data storage that is significantly faster than DRAM memory and which provides consistent access times.
Due to the relatively high cost of cache memories, however, they are typically much smaller than main memory. Consequently, conventional replacement algorithms have been employed to determine what data should be stored in the cache memory. Most of these algorithms fill and replace elements within the cache according to some fixed policy, such that data is rotated in and out of the cache based on this policy.
Occasionally, however, programmers who design applications for these microprocessor systems wish certain critical memory contents to remain in the cache in order to guarantee fixed cycles of latencies to access these critical memory contents. Cache locking allows some or all of the contents of the cache to be locked in place, unsusceptible to the cache replacement policy implemented on the system. This ability to lock the cache is available on several microprocessors, such as the PowerPC, some Intel x86 processors the Motorola MPC7400 etc., and may allow static locking of the cache (cache is loaded and locked at system start) and dynamic locking (the state of the cache may change during execution). While cache locking may decrease the performance of the cache, it allows programmers to more accurately predict a worse case access time for a piece of data; particularly important in designing mission critical systems.
Typically, however, the systems and methods utilized to lock the cache may require a large overhead. For example, in one implementation, to lock data elements within the cache a programmer may set the effective address of the data to be locked to a first register for managing a locked cache, and the set information for the set (way) of the cache to be locked to a second register for managing a locked cache. The first access to the effective address (or the virtual address) located in the first register may generate a cache reload to the set (way) of the cache pointed to by the second register. Subsequently, however, the hardware will not replace the cache entry referenced by the second register with other data whose address is different from contents of the second register. Thus, the critical data remains in the cache.
This technique may require that both the effective address and the real address (or the physical address) of data be maintained by the load and store queues of the cache which in turn imposes a heavy hardware penalty. In one implementation, those pair of registers to manage lock addresses is established in an L2 cache unit. For example, if an effective address is fifty-two bits long, the load queue contains four entries and the store queue is eight entries long, to implement this type of cache locking mechanism requires somewhere on the order of 624 bits. The extra flip-flops required to store these bits may occupy a relatively large area on a modern microprocessor.
Thus, a need exists for efficient systems and methods for cache locking mechanisms which reduce the overhead associated with implementing this cache locking.